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d a t a sh eet product speci?cation supersedes data of 2002 dec 04 2004 may 17 integrated circuits pcf8811 80 128 pixels matrix lcd driver
2004 may 17 2 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 pin functions 7.1 row 0 to row 79: row driver outputs 7.2 col 0 to col 127: column driver outputs 7.3 v ss1 and v ss2 : negative power supply rails 7.4 v dd1 to v dd3 : positive power supply rails 7.5 v otpprog : otp programming power supply 7.6 v lcdout , v lcdin and v lcdsense : lcd power supply 7.7 t1 to t5: test pads 7.8 mf2 to mf0 7.9 ds0 7.10 v os4 to v os0 7.11 ext: extended command set 7.12 ps0, ps1 and ps2 7.13 d/ c 7.14 r/ w 7.15 e 7.16 sclh/ sce 7.17 sdah 7.18 sdahout 7.19 db7 to db0 7.20 osc: oscillator 7.21 res: reset 8 block diagram functions 8.1 oscillator 8.2 address counter (ac) 8.3 display data ram (ddram) 8.4 timing generator 8.5 display address counter 8.6 lcd row and column drivers 9 addressing 9.1 display data ram structure 10 parallel interface 10.1 6800 series parallel interface 11 serial interfacing (spi and serial interface) 11.1 serial peripheral interface 11.2 serial interface (3-line) 12 i 2 c-bus interface 12.1 characteristics of the i 2 c-bus (hs-mode) 12.2 i 2 c-bus hs-mode protocol 12.3 command decoder 13 instructions 13.1 explanation of the symbols 13.2 initialization 13.3 reset function 13.4 power-save mode 13.5 display control 13.6 set y address of ram 13.7 set x address of ram 13.8 set display start line 13.9 bias levels 13.10 set v op value 13.11 temperature control 14 limiting values 15 handling 16 dc characteristics 17 ac characteristics 18 parallel interface timing characteristics 19 serial interface timing characteristics 20 i 2 c-bus interface timing characteristics 21 application information 22 module maker programming 22.1 v lcd calibration 22.2 temperature coefficient selection 22.3 seal bit 22.4 otp architecture 22.5 interface commands 22.6 example of filling the shift register 22.7 programming flow 22.8 programming specification 23 chip information 24 bonding pad locations 25 device protection diagram 26 tray information 27 data sheet status 28 definitions 29 disclaimers 30 purchase of philips i 2 c components
2004 may 17 3 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 1 features single-chip lcd controller/driver 80 row and 128 column outputs display data ram 80 128 bits 128 icons (row 80 can be used for icons in extended command set and when icon rows are enabled) an 8-bit parallel interface, 3 or 4-line serial peripheral interface (spi) and high-speed i 2 c-bus on-chip: C configurable voltage multiplier generating v lcd ; external v lcd also possible C linear temperature compensation of v lcd ; 8 programmable temperature coefficients (extended command set); one fixed temperature coefficient which default can be set by otp programming (basic command set) C generation of intermediate lcd bias voltage C oscillator requires no external components; external clock input also possible. otp calibration for v lcd and accurate frame frequency external reset input pin cmos compatible inputs mux rate: 1 : 16 to 1 : 80 in steps of 8 when no icon row is used, with the icon row steps of 16 can be used logic supply voltage range v dd1 - v ss : C 1.7 v to 3.3 v. high voltage generator supply voltage range v dd2 ,v dd3 - v ss : C 1.8 v to 3.3 v. display supply voltage range v lcd - v ss : C 3vto9v. low power consumption; suitable for battery operated systems programmable bottom row pads mirroring; for compatibility with both tape carrier packages (tcp) and chip on glass (cog) applications (extended command set) status read which allows for chip recognition and content checking of some registers start address line which allows, for instance, the scrolling of the displayed image programmable display ram pointers for variable display sizes slim chip layout, suited for cog applications temperature range: t amb = - 40 c to +85 c. 2 applications telecom equipment portable instruments point of sale terminals. 3 general description the pcf8811 is a low power cmos lcd controller driver, designed to drive a graphic display of 80 rows and 128 columns or a graphic display of 79 rows and 128 columns and a icon row of 128 symbols. all necessary functions for the display are provided in a single chip, including on-chip generation of the lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. the pcf8811 can interface to microcontrollers via a parallel bus, serial bus or i 2 c-bus interface. 4 ordering information type number package name description version pcf8811u/2da/1 - chip with bumps in tray, not covered under philips/motif license agreement - pcf8811mu/2da/1 - chip with bumps in tray, sold under license from motif -
2004 may 17 4 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 5 block diagram mgw732 display data ram 80 128 bits data processing column drivers orthogonal function generator reset row drivers col 0 to col 127 pcf8811 row 0 to row 79 128 t1 t2 t3 t4 t5 timing generator address counter command decoder display address counter oscillator osc i/o buffer parallel / serial / i 2 c-bus interface db7/sdata db6/sclk db5/sdo db4 db3/sa1 db2/sa0 db1 db0 v lcdout v lcdsense v lcdin ext e sdah sdahout v ss2 v otpprog v ss1 v dd1 v dd2 v dd3 high voltage generator bias voltage generator res 80 3 5 mf [ 2:0 ] ps [ 2:0 ] v os [ 4:0 ] 3 ds0 d/c r/w sclh/sce fig.1 block diagram.
2004 may 17 5 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 6 pinning symbol pad description mf2 9 manufacturer device id input mf1 10 manufacturer device id input mf0 11 manufacturer device id input ds0 12 device recognition input osc 13 oscillator input ext 14 extended command set input ps0 15 parallel/serial/i 2 c-bus data selection input ps1 16 parallel/serial/i 2 c-bus data selection input ps2 17 parallel/serial/i 2 c-bus data selection input v ss(tie off) 18 sdahout 19 i 2 c-bus data output sdah 20 and 21 i 2 c-bus data input sclh/ sce 22 and 23 i 2 c-bus clock input/ chip enab le (6800 interface) v otpprog 24 to 26 supply voltage for otp programming (can be combined with sclh/ sce) res 27 external reset input d/ c 28 data/ command input r/ w 29 read/ wr ite (6800 interface) input e 30 clock enable (6800 interface) input v dd(tie off) 31 db0 32 parallel data input/output db1 33 parallel data input/output db2/sa0 34 parallel data input/output or i 2 c-bus slave address input db3/sa1 35 parallel data input/output or i 2 c-bus slave address input db4 36 parallel data input/output db5/sdo 37 parallel data input/output or serial data output db6/sclk 38 parallel data input/output or serial clock input db7/sdata 39 parallel data input/output or serial data input v dd1 40 to 45 general supply voltage v dd2 46 to 55 supply voltage for the internal voltage generator v dd3 56 to 60 supply voltage for the internal voltage generator v ss1 61 to 70 ground v ss2 71 to 80 ground t5 81 test input 5 t2 82 test input 2 t1 83 test input 1 t4 84 test output 4 t3 85 test output 3 v os4 86 v lcd offset input pad 4 v os3 87 v lcd offset input pad 3 v os2 88 v lcd offset input pad 2
2004 may 17 6 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 v os1 89 v lcd offset pad 1 v os0 90 v lcd offset pad 0 v lcdout 91 to 99 voltage multiplier output v lcdsense 100 voltage multiplier regulation input v lcdin 101 to 107 lcd supply voltage row 79 to row 40 115 to 154 lcd row driver outputs; row 79 is the icon row when the icon row is enabled row 80 155 duplicate of row 79 col0to col 127 156 to 283 lcd column driver outputs row 0 to row 39 284 to 323 lcd row driver outputs 1, 3 to 8, 109 to 114, 324 to 333 dummy pads 2 and 108 alignment marks symbol pad description 7 pin functions 7.1 row 0 to row 79: row driver outputs these pads output the display row signals. 7.2 col 0 to col 127: column driver outputs these pads output the display column signals. 7.3 v ss1 and v ss2 : negative power supply rails the 2 supply rails must be connected together. 7.4 v dd1 to v dd3 : positive power supply rails v dd2 and v dd3 are the supply voltage for the internal voltage generator. both have the same voltage and may be connected together outside of the chip. v dd1 is used as supply for the rest of the chip. v dd1 can be connected together with v dd2 , v dd3 but in this case care must be taken to respect the supply voltage range; see chapter 16. if the internal voltage generator is not used then pins v dd2 and v dd3 must be connected to v dd1 . 7.5 v otpprog : otp programming power supply supply voltage for the otp programming; see chapter 22. v otprog can be combined with the sclh/ sce pin in order to reduce the external connections. 7.6 v lcdout , v lcdin and v lcdsense : lcd power supply positive power supply for the liquid crystal display. if the internal v lcd generator is used, then all three inputs must be connected together. if not (v lcd generator is disabled and an external voltage is supplied to v lcdin ), then v lcdout must be left open-circuit, v lcdsense must be connected to v lcdin , v dd2 and v dd3 should be applied according to the specified voltage range. an external lcd supply voltage can be supplied using the v lcdin pad. in this case, v lcdout should not be connected to v lcdin , and the internal voltage generator must be switched off. if the pcf8811 is in power-save mode, the external lcd supply voltage can be switched off. 7.7 t1 to t5: test pads t1, t2 and t5 must be connected to v ss , t3 and t4 must be left open-circuit. not accessible to user. 7.8 mf2 to mf0 manufacturer device id pads. (manufacturer id 100 = philips). 7.9 ds0 device recognition pad; see table 10.
2004 may 17 7 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 7.10 v os4 to v os0 these 5 input pins enable the calibration of the programmed v lcd (can be connected on the module to v dd1 or v ss1 ). 7.11 ext: extended command set input to select the basic command set or the extended command set. must be connected on the module to have only one command set enabled. table 1 command set note: philips strongly recommends that the extended command set be used. 7.12 ps0, ps1 and ps2 parallel/serial/i 2 c-bus interface selection. table 2 interface selection 7.13 d/ c input to select either command/data or data input. not used in the 3-line serial interface, 3-line spi and i 2 c-bus interface and must be connected to v dd1 or v ss1 . 7.14 r/ w input to select read or write mode when the 6800 parallel interface is selected. not used in the serial and i 2 c-bus mode and must be connected to v dd1 or v ss1 . 7.15 e e is the clock enable input for the 6800 parallel bus. not used in the serial or i 2 c-bus interface and must be connected to v dd1 or v ss1 . 7.16 sclh/ sce input to select the chip and so allowing data/ commands to be clocked in or serial clock input when the i 2 c-bus interface is selected. 7.17 sdah i 2 c-bus serial data input. when not used it must be connected to v dd1 and v ss1 . 7.18 sdahout sdahout is the serial data acknowledge output for the i 2 c-bus interface. by connecting sdahout to sdah externally, the sdah line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in cog applications. in cog applications where the track resistance from the sdahout pad to the system sdah line can be significant, a potential divider is generated by the bus pull-up resistor and the ito track resistance. it is possible that during the acknowledge cycle the pcf8811 will not be able to create a valid logic 0 level. by splitting the sdah input from the sdahout output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdahout pad to the system sdah line to guarantee a valid low level. when not used it must be connected to v dd1 or v ss1 . 7.19 db7 to db0 these input/output lines are used by the several interfaces as described below. when not used in the serial interface or the i 2 c-bus interface it must be connected to v dd1 or v ss1 . 7.19.1 db7 to db0 ( parallel interface ) 8-bit bidirectional bus. db7 is the msb. 7.19.2 db7, db6 and db5 ( serial interface ) db7 is used for serial input data (sdata) when the serial interface is selected. db6 (sclk) is used for the serial input clock when the serial interface is selected. db5 is used as the serial output of the serial interface (sdo). 7.19.3 db3 and db2 (i 2 c- bus interface ) db3 and db2 are respectively the sa1 and sa0 inputs when the i 2 c-bus interface is selected and can be used so that up to four pcf8811s can be distinguished on one i 2 c-bus interface. pin level description ext low basis command set high extended command set ps[2:0] interface 000 3-line spi 001 4-line spi 010 no operation 011 6800 parallel interface 100 or 110 high-speed i 2 c-bus interface 101 or 111 3-line serial interface
2004 may 17 8 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 7.20 osc: oscillator when the on-chip oscillator is used this input must be connected to v dd1 . an external clock signal, if used, is connected to this input. if the oscillator and external clock are both inhibited by connecting the osc pin to v ss1 , the display is not clocked and may be left in a dc state. to avoid this the chip should always be put into power-down mode before stopping the clock. 7.21 res: reset this signal will reset the device and must be applied to properly initialize the chip. the signal is active low. 8 block diagram functions 8.1 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required and the osc input must be connected to v dd1 . an external clock signal, if used, is connected to this input. 8.2 address counter (ac) the address counter assigns addresses to the display data ram for writing. the x address x[6:0] and the y address y[3:0] are set separately. 8.3 display data ram (ddram) the pcf8811 contains an 80 128-bit static ram which stores the display data. the ram is divided into 10 banks of 128 bytes (10 8 128 bits). the icon row when enabled is always row 79 and therefore located in bank 9. during ram access, data is transferred to the ram via the parallel, serial interface or i 2 c-bus interface. there is a direct correspondence between the x address and the column output number. 8.4 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not affected by operations on the data bus. 8.5 display address counter the display is generated by simultaneously reading out the ram content for 2, 4 or 8 rows depending on the selected current display size. this content will be processed with the corresponding set of 2, 4 or 8 orthogonal functions and so generating the signals for switching the pixels in the display on or off according to the ram content. the possibility exists to set the p value for the display sizes 64 and 80 manually to p = 4. the display status (all dots on/off and normal/inverse video) is set by the bits don, dal and e in the command display control; see table 6. 8.6 lcd row and column drivers the pcf8811 contains 80 row and 128 column drivers, which connect the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed.
2004 may 17 9 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 top of lcd mgw734 dpram bank 0 bank 1 bank 2 r0 r8 r16 r24 r72 r79 bank 3 bank 9 lcd fig.2 ddram to display mapping.
2004 may 17 10 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 9 addressing data is downloaded in bytes into the ram matrix of the pcf8811 as indicated in fig.2. the display ram has a matrix of 80 by 128 bits. the columns are addressed by the address pointer. the address ranges are: x=0to127 (1111111), y = 0 to 9 (1001). the y address represents the bank number. the x and y address which are effectively used can be programmed thus in order to use the pcf8811 with different display sizes without additional loading of the microprocessor. addresses outside these ranges are not allowed. the icon row when enabled is always row 79 and therefore located in bank 9. 9.1 display data ram structure the mode for storing data into the data ram is dependent on the selected command set. 9.1.1 b asic command set after a write operation the column address counter (x address) auto-increments by one, and wraps to zero after the last column is written. the number of columns (x address) after which the wrap around must occur can be programmed. the y address counter does not auto-increment in the basic command set, the counter stops when a complete bank has been written to. in this case the y address counter must be set (y address see table 5) to write the next bank (see fig.3). when only a part of the ram is used both x (x max) and y (y max) addresses can be set. the data order in the basic command set is as defined in fig.3. handbook, full pagewidth mgw735 0 y max 0 x max x address y address lsb msb lsb msb fig.3 sequence of writing data bytes into the ram (basic command set).
2004 may 17 11 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 9.1.2 e xtended command set 9.1.2.1 horizontal/vertical addressing two different addressing modes are possible with the extended command set: horizontal addressing mode and vertical addressing mode. in the horizontal addressing mode (v = 0) the x address increments after each byte. after the last x address, x wraps around to 0 and y increments to address the next row (see fig.4). the number of columns (last x address) after which the wrap around must occur can be programmed. in fig.4 it can be seen that the x address is programmed to be 127, and the y address is programmed to be 9. with x max and y max the x and y addresses can be programmed while the whole ram is not being used. in the vertical addressing mode (v = 1) the y address increments after each byte. after the last y address (y = 9), y wraps around to 0 and x increments to address the next column (see fig.5). the last y address after which y wraps to 0 can be programmed. in fig.5 it can be seen that the x address is programmed to be 127, and the y address is programmed to be 9. with x max and y max the x and y addresses can be programmed while the whole ram is not being used. after the very last address the address pointers wrap around to address x = 0 and y = 0 in both horizontal and vertical addressing modes. handbook, full pagewidth mgw736 012 128 129 130 256 257 258 384 385 386 512 513 514 640 641 642 0 9 0 127 x address y address 768 769 770 896 897 898 1024 1025 1026 1152 1153 1154 1279 fig.4 sequence of writing data bytes into ram with horizontal addressing (v = 0) (extended command set).
2004 may 17 12 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw737 010 111 2 3 4 5 0 9 0 127 x address y address 6 7 8 9 1279 fig.5 sequence of writing data bytes into the ram with vertical addressing (v = 1) (extended command set). 9.1.2.2 data order the data order bit (dor) defines the bit order (lsb or msb on top) for writing into the ram (see figs 6 and 7). this feature is only available in the extended command set. handbook, full pagewidth mgw738 lsb msb lsb msb fig.6 ram byte organisation, if dor = 0 (extended command set).
2004 may 17 13 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 9.1.3 f eatures available in both command sets 9.1.3.1 mirror x (mx) the mx bit allows horizontal mirroring: when mx = 1 the x address space is mirrored; the address x = 0 is then located at the right side (x max) of the display (see fig.8). when mx = 0 the mirroring is disabled and the address x = 0 is located at the left side (column 0) of the display (see fig.9). handbook, full pagewidth mgw739 msb lsb msb lsb fig.7 ram byte organisation, if dor = 1 (extended command set). handbook, full pagewidth mgw740 0 y max 0 x max x address y address fig.8 ram format addressing (mx = 1) (both command sets).
2004 may 17 14 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 9.1.3.2 mirror y (my) the my bit allows vertical mirroring: when my = 1 the y address space is mirrored; the address y = 0 is then located at the bottom of the display (see fig.10). when my = 0 the mirroring is disabled and the address y = 0 is located at top of the display (see fig.11). the icon row, when enabled, will always be located in bank 9 and row 79. handbook, full pagewidth mgw741 0 y max 0 x max x address y address fig.9 ram format addressing (mx = 0) (both command sets). handbook, full pagewidth mgw742 0 y max 0 x max x address y address fig.10 ram format addressing (my = 1) (both command sets).
2004 may 17 15 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw743 0 y max 0 x max x address y address fig.11 ram format addressing (my = 0) (both command sets). 10 parallel interface the parallel interfaces which can be selected is the 6800 series 8-bit bidirectional interface for communication between the microcontroller and the lcd driver chip. the selection of these interfaces is achieved with pins ps[2:0]; see section 7.12. 10.1 6800 series parallel interface the interface functions of the 6800 series parallel interface are given in table 3. table 3 6800 series parallel interface function the parallel interface timing diagram for the 6800 series is given in chapter 18 (see figs 35 and 36). the timing diagrams differ because the clock is connected (in fig.35) to the enable (e) input. in fig.36 the clock is connected to the chip select input ( sce) and the enable input (e) is tied high. d/ cr/ wr operation 0 0 command data write 0 1 read status register 1 0 display data write 1 1 none
2004 may 17 16 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 11 serial interfacing (spi and serial interface) communication with the microcontroller can also occur via a clock-synchronized serial peripheral interface (spi). it is possible to select two different 3-line (spi and serial interface) or a 4-line serial interface. selection is achieved via ps[2:0]; see section 7.12. 11.1 serial peripheral interface the serial peripheral interface is a 3-line or 4-line interface for communication between the microcontroller and the lcd driver chip. the 3 lines are: sce (chip enable), sclk (serial clock) and sdata (serial data). for the 4-line serial interface a separate d/ c line is added. the pcf8811 is connected to the serial data i/o (sda) of the microcontroller by two pins: sdata (data input) and sdo (data output) connected together. 11.1.1 w rite mode the display data/ command indication may be controlled either via software or the d/ c select pin. when the d/ c pin is used, display data is transmitted when d/ c is high, and command data is transmitted when d/ c is low (see figs 12 and 13). when pin d/ c is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 255) are to be transmitted (see fig.14). the next byte after the display data string is handled as an instruction command. when the 3-line spi interface is used the display data/ command is controlled by software. if sce is pulled high during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. the next byte received will be handled as an instruction command (see fig.15). handbook, full pagewidth sce d/c sclk sdata db7 db6 db5 db4 db3 db2 db1 db0 mgw744 fig.12 serial bus protocol: transmission of one byte. handbook, full pagewidth sce d/c sclk sdata db7 db6 db5 db4 db3 db2 db1 db0 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 mgw745 fig.13 serial bus protocol: transmission of several bytes.
2004 may 17 17 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth sce sclk sdata db7 db6 db5 db4 display length instruction and length data (two bytes) db2 db1 db0 db2 data data last data db7 db6 db5 db4 db3 db1 db0 mgw746 instruction display data string fig.14 transmission of several bytes. handbook, full pagewidth mgw747 sce sclk sdata data data data data data data db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 db4 instruction display data string fig.15 transmission interrupted by sce. 11.1.2 r ead mode ( only extended command set ) the read mode of the interface means that the microcontroller reads data from the pcf8811. to do so the microcontroller first has to send a command (the read status command) and then the pcf8811 will respond by transmitting data on the sdo line. after that sce is required to go high (see fig.16). the pcf8811 samples the sdin data on rising sclk edges, but shifts sdo data on falling sclk edges. thus the microcontroller is supposed to read sdo data on rising sclk edges. after the read status command has been sent, the sdin line must be set to 3-state not later then the falling sclk edge of the last bit (see fig.16). the serial interface timing diagram is given in chapter 19.
2004 may 17 18 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth res sclk sdata db7 db6 db5 db4 db2 db3 db1 db0 sdo instruction db2 db7 db6 db5 db4 db3 db1 db0 mgw748 read out data sce fig.16 read mode spi 3-line and 4-line. 11.2 serial interface (3-line) the serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the lcd driver chip. the 3 lines are: sce (chip enable), sclk (serial clock) and sdata (serial data). the pcf8811 is connected to the sda of the microcontroller by two pins: sdata (data input) and sdo (data output) which are connected together. 11.2.1 w rite mode the write mode of the interface means that the microcontroller writes commands and data to the pcf8811. each data packet contains a control bit (d/ c) and a transmission byte. if d/ c is low, the following byte is interpreted as a command byte. the command set is given in table 5. if d/ c is high, the following byte is stored in the display data ram. after every data byte the address counter is incremented automatically. figure 17 shows the general format of the write mode and the definition of the transmission byte. any instruction can be sent in any order to the pcf8811; the msb is transmitted first. the serial interface is initialized when sce is high. in this state, sclk clock pulses have no effect and no power is consumed by the serial interface. a falling edge on sce enables the serial interface and indicates the start of data transmission. figures 18, 19 and 20 show the protocol of the write mode: when sce is high, sclk clocks are ignored; during the high time of sce the serial interface is initialized sclk must be low on the falling sce edge (see fig.37) sdata is sampled on the rising edge of sclk d/ c indicates, whether the byte is a command (d/ c=0) or ram data (d/ c = 1); it is sampled on the first rising sclk edge if sce stays low after the last bit of a command/data byte, the serial interface receives the d/ c bit of the next byte on the next rising edge of sclk (see fig.19) a reset pulse res interrupts the transmission. the data being written into the ram may be corrupted. the registers are cleared. if sce is low after the rising edge of res, the serial interface is ready to receive the d/ c bit of a command/data byte (see fig.20).
2004 may 17 19 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth d/c db7 db6 db5 db4 db3 transmission byte (tb) (command byte or data byte) db2 db1 db0 msb lsb mgu278 tb d/c tb d/c tb d/c fig.17 serial data stream; write mode. handbook, full pagewidth sce d/c sclk sdin db7 db6 db5 db4 db3 db2 db1 db0 mgu279 fig.18 write mode: a control bit followed by a transmission byte. handbook, full pagewidth sce sclk sdin db7 d/c db6 db5 db4 db3 db2 db1 db0 mgu280 db7 d/c db6 db5 db4 db3 db2 db1 db0 d/c fig.19 write mode: transmission of several bytes.
2004 may 17 20 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgu281 sce res sclk sdin db7 d/c db6 db5 db4 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 d/c d/c fig.20 write mode: interrupted by reset ( res). 11.2.2 r ead mode ( only extended command set ) the read mode of the interface means that the microcontroller reads data from the pcf8811. to do so the microcontroller first has to send a command (the read status command) and then the following byte is transmitted in the opposite direction (using sdo) (see fig.21). after that, sce is required to go high before a new command is sent. the pcf8811 samples the sdata data on the rising sclk edges, but shifts sdo data on the falling sclk edges. thus the microcontroller is supposed to read sdo data on rising sclk edges. after the read status command has been sent, the sdata line must be set to 3-state not later then the falling sclk edge of the last bit (see fig.21). the 8th read bit is shorter than the others because it is terminated by the rising sclk edge (see fig.40). the last rising sclk edge sets sdo to 3-state after the delay time t4. the serial interface timing diagram is given in chapter 19. handbook, full pagewidth mgu282 sce sclk sdin sdout db7 d/c db6 db5 db4 db7 db6 db5 db4 db3 db2 db1 db0 db3 db2 db1 db0 d/c fig.21 read mode serial interface 3-line.
2004 may 17 21 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 12 i 2 c-bus interface 12.1 characteristics of the i 2 c-bus (hs-mode) the i 2 c-bus hs-mode is for bidirectional, two-line communication between different ics or modules with speeds of up to 3.4 mhz. the only difference between hs-mode slave devices and f/s-mode slave devices is the speed at which they operate, therefore the buffers on the sclh and sdah have open-drain outputs. this is the same for i 2 c-bus master devices which have an open-drain sdah output and a combination of an open-drain, pull-down and current source pull-up circuits on the sclh output. only the current source of one master is enabled at any one time, and only during hs-mode. both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 12.1.1 s ystem configuration the system configuration is illustrated in fig.22. definitions of the i 2 c-bus terminology: transmitter: the device which sends the data to the bus receiver: the device which receives the data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. 12.1.2 b it transfer one data bit is transferred during each clock pulse (see fig.23). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 12.1.3 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are illustrated in fig.24. 12.1.4 a cknowledge each byte of eight bits is followed by an acknowledge bit; see fig.25. the acknowledge bit is a high signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. a master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition.
2004 may 17 22 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.22 system configuration. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.23 bit transfer. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.24 definition of start and stop conditions.
2004 may 17 23 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.25 acknowledge on the i 2 c-bus. 12.2 i 2 c-bus hs-mode protocol the pcf8811 is a slave receiver/transmitter. if data is to be read from the device, the sdah pin must be connected, otherwise sdah may be unused. hs-mode can only commence after the following conditions: start condition (s) 8-bit master code (00001xxx) not-acknowledge bit ( a). the master code has two functions: it allows arbitration and synchronization between competing masters at f/s-mode speeds, resulting in one winner. the master code also indicates the beginning of an hs-mode transfer. these conditions are illustrated in figs 26 and 27. as no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge ( a). after this a bit, and the sclh line has been pulled up to a high level, the active master switches to hs-mode and enables at t h the current-source pull-up circuit for the sclh signal (see fig.27). the active master will then send a repeated start condition (sr) followed by a 7-bit slave address with a r/ w bit, and receives an acknowledge bit (a) from the selected slave. after each acknowledge bit (a) or not-acknowledge bit ( a) the active master disables its current source pull-up circuit. the active master re-enables its current source again when all devices have been released and the sclh signal reaches a high level. the rising of the sclh signal is done by a pull-up resistor and therefore is slower, the last part of the sclh rise time is speeded up because the current source is enabled. data transfer only switches back to f/s mode after a stop condition (p). a write sequence after the hs-mode is selected is illustrated in fig.28. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, the remainder will ignore the i 2 c-bus transfer. after the acknowledgement cycle of a write ( w), one or more command words will follow which define the status of the addressed slaves. a command word consists of a control byte, which defines co and d/ c, plus a data byte (see fig.28 and table 4). the last control byte is tagged with a cleared msb, the continuation bit co. the control and data bytes are also acknowledged by all addressed slaves on the bus.
2004 may 17 24 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 4 co and d/ c de?nition bit logic level r/ w action co 0 n/a last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a stop or re-start condition 1 another control byte will follow the data byte unless a stop or re-start condition is received d/ c 0 0 data byte will be decoded and used to set-up the device 1 data byte will return the status byte 1 0 data byte will be stored in the display ram 1 ram read back is not supported a read sequence is given in fig.29 and again this sequence follows after the hs-mode is selected. the pcf8811 will immediately start to output the requested data until a not-acknowledge is transmitted by the master. before the read access, the user has to set the d/ c bit to the appropriate value by a preceding write access. the write access should be terminated by a re-start condition so that the hs-mode is not disabled. after the last control byte, depending on the d/ c bit setting, either a series of display data bytes or command data bytes may follow. if the d/ c bit was set to logic 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is automatically updated and the data is directed to the intended pcf8811 device. if the d/ c bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. the acknowledgement after each byte is made only by the addressed pcf8811. at the end of the transmission the i 2 c-bus master issues a stop condition (p) and switches back to the f/s-mode, however, to reduce the overhead of the master code, it is possible that a master can link a number of hs-mode transfers, separated by repeated start conditions (sr). handbook, full pagewidth f/s-mode hs-mode (current-source for sclh enabled) f/s-mode msc616 a a a/a data (n bytes + ack.) s r/w master code sr slave add. hs-mode continues sr slave add. p fig.26 data transfer format in hs-mode.
2004 may 17 25 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 msc618 8-bit master code 00001xxx a t h t 1 s fs mode hs-mode if p then fs mode if sr (dotted lines) then hs mode 16789 6789 1 1 2 to 5 2 to 5 2 to 5 67 89 sdah sclh sdah sclh t h t fs sr sr p n (8-bit data + a/a) 7-bit sla r/w a = mcs current source pull-up = rp resistor pull-up fig.27 data transfer timing format in hs-mode. handbook, full pagewidth mgw749 sr01111 s a 0 s a 1 0a acknowledge from pcf8811 acknowledge from pcf8811 acknowledge from pcf8811 acknowledge from pcf8811 acknowledge from pcf8811 1 control byte a data byte data byte n 3 0 bytes 1 byte slave address msb . . . . . . . . . . . lsb 2n 3 0 bytes a co co 0a ap control byte d/c d/c r/w fig.28 master transmits in hs-mode to slave receiver; write mode.
2004 may 17 26 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw750 sr01111 s a 0 s a 1 1a acknowledgement from pcf8811 not acknowledgement from master status information a slave address stop condition p r/w fig.29 master receives from slave transmitter (status register is read); read mode. 12.3 command decoder the command decoder identifies command words that are received on the i 2 c-bus: pairs of bytes: information in 2nd byte, first byte determines whether information is display or instruction data stream of information bytes after co = 0: display or instruction data depending on last d/ c. the most significant bit of a control byte is the continuation bit co. if this bit is at logic 1, it indicates that only one data byte, either command or ram data, will follow. if this bit is at logic 0, it indicates that a series of data bytes, either command or ram data, may follow. the db6 bit of a control byte is the ram data/ command bit d/ c. when this bit is at logic 1, it indicates that a ram data byte will be transferred next. if the bit is at logic 0, it indicates that a command byte will be transferred next. 13 instructions the pcf8811 interfaces via an 8-bit parallel interface, two different 3-line serial interfaces, a 4-wire serial interface or an i 2 c-bus interface. processing of the instructions does not require the display clock. data accesses to the pcf8811 can be broken down into two areas; those that define the operating mode of the device, and those that fill the display ram. in the case of the parallel and 4-wire spi interfaces, the distinction is the d/ c pin. when the d/ c pin is at logic 0, the chip will respond to instructions as defined in table 5. when the d/ c bit is at logic 1, the chip will send data to the ram. when the 3-wire spi, the 3-wire serial interface or the i 2 c-bus interface is used, the distinction between instructions which define the operating mode of the device and those that fill the display ram, is made respectively by the display data length instruction (3-line spi) or by the d/ c bit in the data stream (3-line serial interface and i 2 c-bus interface). there are 4 types of instructions. those which: 1. define the pcf8811 functions, such as display configuration etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, category 3 instructions are used most frequently. a basic and an extended instruction set is available: if the ext pin is set low the basic command set is used. if the ext pin is set high the extended command set is used. both command sets are detailed in table 5.
2004 may 17 27 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 2004 may 17 27 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 5 instruction set; note 1 instruction ext (2) d/ cr/ w command byte description d7 (3) d6 d5 d4 d3 d2 d1 d0 nop x 000 10011xx no operation nop x 001 1100100 no operation reset x 0 0 1 1100010 soft reset write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data to display ram display data length x x 0 0 0 0 1 d7 1 d6 1 d5 0 d4 1 d3 0 d2 0 d1 0 d0 only used in 3-line spi status read x 0 1 busy don res mf2 mf1 mf0 ds1 ds0 read status byte x 0x1 101101x read status byte display control x 0 0 1 010111don display on or off x 001 010011e nor mal or reverse mode x 001 010010dal all pixels on or off x 001 010000mx mirror x x 001 100myxxx mirror y 1 001 110111ic icon enable or disable; note 4 1 001 010001v ver tical or horizontal addressing; note 4 1 001 110101dor data order; note 4 1 001 110110brs bottom row swap; note 4 adr commands x 0 0 1 011y 3 y 2 y 1 y 0 set y address; 0 y 9 x 000 0010x 6 x 5 x 4 set x address; 0 x 127 x 000 000x 3 x 2 x 1 x 0 x0 0 0 0 0 x 0 x 0 x 1 x 1 y max3 0 y max2 0 y max1 1 y max0 set y max; 0 y 9 x 000 x 0 x max6 0 x max5 1 x max4 1 x max3 0 x max2 0 x max1 0 x max0 set x max; 0 x 127 set initial display line x x 0 0 0 0 0 x 1 l 6 0 l 5 0 l 4 0 l 3 0 l 2 x l 1 x l 0 set initial display line; 0 l 79; note 5 set initial row x x 0 0 0 0 0 x 1 c 6 0 c 5 0 c 4 0 c 3 1 c 2 x c 1 x c 0 set start row; 0 c 79; note 6
2004 may 17 28 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 2004 may 17 28 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... set partial display x x 0 0 0 0 0 x 1 p 6 0 p 5 0 p 4 1 p 3 0 p 2 x p 1 x p 0 set partial display 1 : 16 to 1 : 80 v op setting 0 0 0 0 0 0 1 x 0 x 0 v pr5 0 v pr4 0 v pr3 0 v pr2 0 v pr1 1 v pr0 set v op ; notes 7 and 8 0 000 0100v off2 v off1 v off0 offset for the programming range v op ; notes 7 and 8 1 1 0 0 0 0 1 v pr7 0 v pr6 0 v pr5 0 v pr4 0 v pr3 0 v pr2 0 v pr1 1 v pr0 set v op ; note 4 power control x 0 0 0 0101pc 1 pc 0 1 switch hvgen on/off hvgen stages 0 0 0 0 11001s 1 s 0 set multiplication factor 1 000 1100s 2 s 1 s 0 set multiplication factor; note 4 fr 1 000 00111fr 1 fr 0 set frame rate frequency; note 4 tc (9) 1 000 0111tc 2 tc 1 tc 0 set temperature coef?cient; note 4 bias system 0 0 0 0 1010bs 2 bs 1 bs 0 set bias system; note 10 manual p value (p = 4) 1 000 001101mp set manual p value; notes 4 and 11 power-save on x 0 0 1 0101001 pow er-save mode power-save off x 0 0 1 1100001 e xit power-save mode internal oscillator x 0 0 1 010101oss witch internal oscillator on/off internal oscillator 1 0 0 1 110011ec enable or disable the internal or external oscillator; note 4 enter calmm mode x 001 0000010 enter calmm mode reserved x 0 0 0 0101xx0 reserved reserved x 0 0 0 111xxxx reserved test x 001 111xxxx do not use; reserved for testing instruction ext (2) d/ cr/ w command byte description d7 (3) d6 d5 d4 d3 d2 d1 d0
2004 may 17 29 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 notes 1. x = dont care. 2. philips strongly recommends that the extended command set be used. 3. d7 = msb. 4. commands only available with the extended command set, ext = 1. if ext = 0 these commands have no effect. 5. when icon mode is enabled the set initial display line is 0 l 78. 6. when icon mode is enabled the set initial row is 0 c 78. 7. commands only used for the basic command set, ext = 0. if ext = 1 these commands have no effect. care should be taken when setting v op in the basic command set, it must be followed by another command. 8. the programming of v op in the basic command set must be done in the following order: a) v pr [5:0] b) v off [2:0] c) must be followed by another command. 9. one fixed tc is set automatically if the basic command set is used. 10. bias system settings which can be received when the chip is used as replacement of alth and pleskho driving method (nop). 11. only for mux rates 1 : 64 and 1 : 80 the number of simultaneous rows can be manually set to p = 4. 13.1 explanation of the symbols 13.1.1 c ommon i nstructions of the basic and extended command set table 6 explanation of the symbols bit logic 0 logic 1 reset state don display off display on 0 e normal display inverse video mode 0 dal normal display all pixels on 0 mx no x mirroring x mirroring 0 my no y mirroring y mirroring 0 oc stop frame frequency calibration start frame frequency calibration 0 os internal oscillator off start internal oscillator 0 x[6:0] sets x address (column) for writing in the ram 0000000 y[3:0] sets y address (bank) for writing in the ram 0000 xmax[6:0] set wrap around x address (column) 1111111 ymax[3:0] set wrap around y address (bank) 1001 l[6:0] sets line address of the display ram to be displayed on the initial row 0 0000000 c[6:0] sets the initial row 0 of the display; this command cannot access the icon driver row row 80; if icon row is enabled 0000000 p[6:0] partial display mode 1 : 16 to 1 : 80; note 1 1010000 (1 : 80)/1000000 (1 : 64) pc[1:0] switch hv generator on/off 00 s[1:0] charge pump multiplication factor 00
2004 may 17 30 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 note 1. partial displays can be selected in steps of 8 when the icon mode is not selected. when the icon mode is selected partial displays can be selected in steps of 16. for example, without icons the available partial display sizes are 8, 16, 24, 32, 40, 48, 56, 64 or 72 lines. with icons there are 16, 32, 48 or 64 lines possible. table 7 power control table 8 power-save mode (psm), os, don, dal and e combinations; note 1 notes 1. x = dont care. 2. the don bit can only be addressed after dal is activated. 3. the dal bit has priority over the e bit. table 9 read status byte table 10 device recognition; note 1 note 1. this is the only default setting after reset, another setting can be selected with the set partial display mode command. pc[1:0] description 00 hvgen off 01 hvgen on 10 hvgen on 11 hvgen on psm os don dal e description 0 0 x x x oscillator off; hvgen disabled 0 1 x 0 x oscillator on; hvgen enabled 0101x display off, row/col at v ss ; oscillator off; hvgen disabled; note 2 01100nor mal display mode 01101inv erse display mode 0111x all pixels on; note 3 1xxxxpow er-save mode: display off; row/col at v ss ; oscillator off; hvgen disabled bit description busy if busy = 0 the chip is able to accept new commands don same bit as in table 4 res if res = 1 a reset is in progress mf[2:0] device manufacturer id ds0 device recognition; see table 10 ds0 description 0 64 row driver 1 80 row driver
2004 may 17 31 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 11 multiplication settings table 12 v os values in twos complement notation s[1:0] description 00 4 voltage multiplier 01 5 voltage multiplier 10 6 voltage multiplier 11 7 voltage multiplier decimal binary 0 00000 +1 00001 +2 00010 +3 00011 +4 00100 +5 00101 +6 00110 +7 00111 +8 01000 +9 01001 +10 01010 +11 01011 +12 01100 +13 01101 +14 01110 +15 01111 - 1 11111 - 2 11110 - 3 11101 - 4 11100 - 5 11011 - 6 11010 - 7 11001 - 8 11000 - 9 10111 - 10 10110 - 11 10101 - 12 10100 - 13 10011 - 14 10010 - 15 10001 - 16 10000 decimal binary 13.1.2 s pecific commands of the basic command set table 13 explanation of symbols bit logic 0 logic1 reset state v pr [5:0] programming value of v lcd 000000 v off [2:0] offset for the programming value of v lcd 000
2004 may 17 32 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 13.1.3 s pecific commands of the extended command set table 14 explanation of symbols note 1. it is strongly recommended to use the p = 4 setting. bit logic 0 logic 1 reset state v pr [7:6] + v pr [5:0] programming value of v lcd 00000000 fr[1:0] frame-rate frequency 11 tc[2:0] temperature coef?cient (tc2) 010 v horizontal addressing vertical addressing 0 dor lsb at top msb at top 0 ic no icon row (1/16 to 1/80) icon row (1/16 to 1/80) 0 brs bottom rows are not mirrored bottom rows are mirrored 0 mp (1) mux rate driven p value (automatic) p = 4 selected for mux rate 1 : 64 and 1 : 80 0 ec use internal oscillator use external oscillator 0 s[2:0] charge pump multiplication factor 100 table 15 frame-rate frequency table 16 temperature coef?cient table 17 multiplication settings 13.2 initialization reset is accomplished by applying an external reset pulse (active low) at pad res. when reset occurs within the specified time, all internal registers are reset, however the ram is still undefined. the state after reset is described in section 13.3. pad res must be 0.3v dd1 when v dd1 reaches v dd(min) (or higher) within a maximum time t vhrl after v dd1 goes high (see fig.43). a reset can also be achieved by sending a reset command. this command can be used during normal operation but not to initialize the chip after power-on. fr[1:0] frame-rate frequency 00 30 hz 01 40 hz 10 50 hz 11 60 hz tc[2:0] temperature coefficient 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 s[2:0] description 000 2 voltage multiplier 001 3 voltage multiplier 010 4 voltage multiplier 011 5 voltage multiplier 100 4 voltage multiplier 101 5 voltage multiplier 110 6 voltage multiplier 111 7 voltage multiplier
2004 may 17 33 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 13.3 reset function 13.3.1 b asic command set after reset the lcd driver has the following state: display setting e = 0 and dal = 0 address commands x[6:0] = 0 and y[3:0] = 0 v lcd is equal to 0, the hv generator is switched off (pc[1:0] = 00) no offset of the programming range (v off [2:0] = 0) hv generator programming (v pr [5:0] = 0) 4 voltage multiplier (s[1:0] = 00) after power-on, ram data is undefined, the reset signal does not change the content of the ram all lcd outputs at v ss (display off) initial display line set to line 0 (l[6:0] = 0) initial row set to row 0 (c[6:0] = 0) full display selected (p[6:0] = mux 1 : 80 or 1 : 64) display is not mirrored (mx = 0 and my = 0) internal oscillator is off power-save mode is on no frame calibration is running. 13.3.2 e xtended command set after reset the lcd driver has the following state: display settings e = 0 and dal = 0 icons disabled (ic = 0) address counter x[6:0] = 0 and y[3:0] = 0 temperature control mode tc2 (tc[2:0] = 010) v lcd is equal to 0; the hv generator is switched off (pc[1:0] = 0) hv generator programming (v pr [7:0] = 0) 4 voltage multiplier (s[2:0] = 100) frame-rate frequency (fr[1:0] = 11) after power-on, ram data is undefined, the reset signal does not change the content of the ram all lcd outputs at v ss (display off) full display selected (p[6:0] = mux 1 : 80 or 1 : 64) initial display line set to line 0 (l[6:0] = 0) initial row set to row 0 (c[6:0] = 0) display is not mirrored (mx = 0; my = 0) internal oscillator is off power-save mode is on horizontal addressing enabled (v = 0) no data order swap (dor = 0) no bottom row swap (brs = 0) internal oscillator enabled (ec = 0) no frame calibration running (oc = 0). 13.4 power-save mode in the power-save mode the lcd driver has the following state: all lcd outputs at v ss (display off) bias generator and v lcd generator switched off; external v lcd can be disconnected oscillator off (external clock possible) ram contents not cleared; ram data can be written v lcd discharged to v ss in power-down mode. there are two ways to put the chip into power-save mode: the display must be off (don = 0) and all the pixels on (dal = 1) the power-save mode command is activated. 13.5 display control the bits don, e and dal select the display mode; see table 8. 13.5.1 mx when mx = 0 the display ram is written from left to right (x = 0 is on the left side and x = x max is on the right side of the display). when mx = 1 the display ram is written from right to left (x = 0 is on the right side and x = x max is on the left side of the display). the mx bit has an impact on the way the ram is written to. so if a horizontal mirroring of the display is desired, the ram must first be rewritten, after changing the mx bit. 13.5.2 my when my = 1, the display is mirrored vertically. a change of this bit has an immediate effect on the display.
2004 may 17 34 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 13.6 set y address of ram y[3:0] defines the y address of the display ram. table 18 x/y address range when the icon row is enabled this icon row (row 79) will always be in bank 9 independent of the mux rate which is programmed. 13.7 set x address of ram the x address points to the columns. the range of x is 0 to 127 (7fh). 13.8 set display start line l[6:0] is used to select the display line address of the display ram to be displayed on the initial row, row 0. the selection of l is limited to steps of 8. when the icon row is selected, the selection of l is limited to steps of 16. when a partial mode is selected, the selection of l is also limited in steps. in addition, the selection of l = 72 is not allowed when the icon row is enabled or disabled. the initial row can, in turn, be set by c[6:0]. row 0 cannot be set to the icon row row 79 when enabled. an example of the mapping from the ram content to the display is illustrated in fig.30. the content of the ram is not modified. this feature allows, for instance, screen scrolling without rewriting the ram. y3 y2 y1 y0 content allowed x range 0000 bank 0 (display ram) 0 to 127 0001 bank 1 (display ram) 0 to 127 0010 bank 2 (display ram) 0 to 127 0011 bank 3 (display ram) 0 to 127 0100 bank 4 (display ram) 0 to 127 0101 bank 5 (display ram) 0 to 127 0110 bank 6 (display ram) 0 to 127 0111 bank 7 (display ram) 0 to 127 1000 bank 8 (display ram) 0 to 127 1001 bank 9 (display ram) 0 to 127
2004 may 17 35 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 mgw751 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 row 3 row 1 row 0 row 2 row 7 row 5 row 4 row 6 row 11 row 9 row 8 row 10 row 15 row 13 row 12 row 14 row 23 row 21 row 20 row 22 row 27 row 25 row 24 row 26 row 31 row 29 row 28 row 30 row 67 row 65 row 64 row 66 row 19 row 17 row 16 row 18 row 71 row 69 row 68 row 70 row 75 row 73 row 72 row 74 row 79 row 77 row 76 row 78 l = 8 c = 16 ram display 0 x address set initial display line and start row when my = 0 1 2 3 8 9 fig.30 programming the l address and c address when my = 0.
2004 may 17 36 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 13.9 bias levels the bias levels for an mra driving method with p = 8 are given in fig.31 when g max and f have the same value. the value p defines the number of rows which are simultaneously selected. the row voltage f depends on the mux rate selected (number of rows n), the threshold voltage of the liquid (v th ), the number of simultaneously selected rows (p) and the multiplexibility (m): (1) the column voltages are situated around the common level v c . the column voltage levels are equidistant from each other. in table 19 the column voltage levels are given as a function of f. handbook, full pagewidth mgw752 v c 0.25g max 0.50g max 0.75g max g max = f = v lcd v lcd v3_h v2_h v1_h v c v1_l v2_l v3_l v ss - g max = f = v ss - 0.25g max - 0.50g max - 0.75g max fig.31 bias levels for a mra system with p = 8 and g max =f. f 1 p ------- v th n 2 --- - mmn C m1 C -------------------------------- =
2004 may 17 37 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 19 bias levels for mra driving method symbol bias voltages dc shifted bias voltages f=g max v lcd fv lcd v3_h v2_h v1_h v c 0 1 / 2 v lcd v1_l v2_l v3_l v ss - fv ss p2 C () f mmn C C ---------------------------------- v lcd 2 ------------- 1 p2 C () mmn C C ---------------------------------- + ? ?? p4 C () f mmn C C ---------------------------------- v lcd 2 ------------- 1 p4 C () mmn C C ---------------------------------- + ? ?? p6 C () f mmn C C ---------------------------------- v lcd 2 ------------- 1 p6 C () mmn C C ---------------------------------- + ? ?? p6 C () C f mmn C C ---------------------------------- v lcd 2 ------------- 1 p6 C () mmn C C ---------------------------------- C ? ?? p4 C () C f mmn C C ---------------------------------- v lcd 2 ------------- 1 p4 C () mmn C C ---------------------------------- C ? ?? p2 C () C f mmn C C ---------------------------------- v lcd 2 ------------- 1 p2 C () mmn C C ---------------------------------- C ? ?? the row voltages (f) are not necessarily larger then the column voltages. this depends on the number of rows which are selected, the multiplexibility and the value of p. however, the pcf8811 is designed in such a way that the maximum column voltages are always equal to the row voltages. in table 20 the v lcd and the different bias levels are given for the pcf8811. the v lcd voltage is defined as: (2) where f is defined in (1) the bias system settings for different display modes are given in table 20. all bias levels can be calculated by using the third column of table 19 and the variables given in table 20. programming of the bias levels is not necessary in the pcf8811. the selection of the appropriate bias level voltages for each display mode is done automatically. only the appropriate v lcd voltage must be programmed according to equations (1) and (2) for the display modes listed in table 20. the variables for calculating v lcd , when the icon row is enabled, are given in table 21. the icon row can only be addressed in the extended command set. the pcf8811 allows the value of p, for certain mux rates, to be chosen manually. this is only possible for the mux rates 1 : 64 and 1 : 80. if other mux rates are chosen the pcf8811 determines the optimum value of p. by setting the value of p manually a compromise can be made between contrast and power consumption with certain liquids for the high mux rates 1 : 64 and 1 : 80. however, care must be taken that the liquid which is chosen ensures that the row voltages (f) and the maximum column voltages are equal. table 20 relationship between mux rates and bias setting variables without icon row v lcd 2f = mux rate n m p 1:16 16 25 2 1:24 24 49 2 1:32 32 81 2 1:40 40 49 4 1:48 48 64 4 1:56 56 81 4 1:64 64 64 8 1:72 72 81 8 1:80 80 81 8
2004 may 17 38 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 21 relationship between mux rates and bias setting variables with the icon row (only extended command set) 13.10 set v op value for mux rate 1 : 80 the optimum operation voltage of a liquid can be calculated with the variables given in table 21 and equations (1) and (2). (3) where v th is the threshold voltage of the liquid crystal material used. the way of programming the v op value is implemented differently in the basic command set in comparison to the extended command set. in the basic command set two commands are sent to the pcf8811: namely v pr [5:0] and v off [2:0]. in the extended command set only one command v pr [7:0] is sent to the pcf8811. this v op programming is illustrated in fig.32. the programming of v op in the basic command set can be used when the pcf8811 is used as a replacement for an iapt lcd driver. a conversion table (rom) can be provided which transfers the programming of an iapt v op value to a mra v op value. mux rate n m p 1:16 24 49 2 1:32 40 49 4 1:48 56 81 8 1:64 80 81 8 1:80 80 81 8 v lcd 2 8 ------- v th 80 2 ------ 81 81 80 C C 81 1 C --------------------------------------- - 4.472 v th = = handbook, full pagewidth mgw753 v lcd look-up table rom 1 0 mmvopcal [ 4:0 ] v os [ 4:0 ] v op [ 7:0 ] v pr [ 7:0 ] rom_add[8:0] v pr [ 5:0 ] v off [ 2:0 ] b ext ext = 1 ext = 0 a 7 6 5 4 3 2 1 0 2 1 0 fig.32 setting of v op in the basic and extended command set.
2004 may 17 39 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 13.10.1 b asic command set the v lcd at t = t cut in the basic command set is determined by the conversion in the rom look-up table with the programmed values of v pr [5:0] and v off [2:0]. it can, additionally, be adjusted with the v lcd offset pads v os [4:0] to obtain the optimum optical performance. instead of using the v lcd offset pads (v op [4:0]) the v lcd can be adjusted with the module maker calibration setting mmvopcal[4:0]; see chapter 22. (4) where: t cut is a reference temperature; see section 13.11 a is a fixed constant value; see table 22 b is a fixed constant value; see table 22 v op [7:0] is the result of the conversion table v os [4:0]/mmvopcal[4:0] is the value of the offset v lcd offset pads or the value stored in the otp cells. table 22 parameters of v lcd for the basic and extended command set 13.10.2 e xtended c ommand set the v lcd at t = t cut can be calculated with equation (5). in the extended command set v pr [7:0] is the same value as v op [7:0]. it can additionally be adjusted with the v lcd offset pads v os [4:0] to obtain the optimum optical performance. instead of using the v lcd offset pads (v op [4:0]) the v lcd can be adjusted with the module maker calibration setting mmvopcal[4:0]; see chapter 22. (5) where: t cut is a reference temperature (see section 13.11) a is a fixed constant value (see table 22) b is a fixed constant value (see table 22) v pr [7:0] is the programmed v op value v os [4:0]/mmvopcal[4:0] is the value of the offset v lcd offset pads or the value stored in the otp cells. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd (9 v) the user has to ensure while setting the v pr register and selecting the temperature compensation (tc), that under all conditions and including all tolerances the v lcd remains below 9.0 v. this is valid for the two different command sets. symbol value unit t cut 40 c b 0.03 v a3v v lcd tt cut = () av os [4:0] v op [7:0] + () b + = v lcd tt cut = () av os [4:0] v pr [7:0] + () b + =
2004 may 17 40 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgt847 00 01 02 a v lcd v op 03 04 05 06 . . . . . . fd fe ff b fig.33 v lcd programming of pcf8811. v op [7:0] programming, (00h to ffh). 13.11 temperature control due to the temperature dependency of the liquid crystals viscosity the lcd controlling voltage v lcd might have to be increased at lower temperature to maintain optimum contrast. the v lcd at a specific temperature is calculated as follows for both command sets. v lcd (at t = t cut ) is given by equations (4) or (5), depending on the command set which is used. (6) in the extended command set and basic command set 8 different temperature coefficients are available (see fig.34). the typical values of the different temperature coefficients are given in chapter 16. the coefficients are proportional to the programmed v lcd . the basic and extended command set differ in the way that the temperature coefficients can be accessed. in the basic command set only one temperature coefficient is available. however, the possibility exists to program the default temperature coefficient by means of otp programming; see chapter 22. in the extended command set the different temperature coefficients are selected by the interface with three bits tc[2:0]. v lcd t () v lcd tt cut = () 1tt cut C () tc + [] = handbook, halfpage mgw754 v lcd t cut t fig.34 temperature coefficients.
2004 may 17 41 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 14 limiting values in accordance with the absolute maximum rating system (iec 60134); notes 1 and 2. notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are referenced to v ss unless otherwise specified. 15 handling inputs and outputs are protected against electrostatic discharge in normal handling. however it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd1 general supply voltage - 0.5 +6.5 v v dd2, v dd3 supply voltage for the internal voltage generator - 0.5 +4.5 v v lcd lcd supply voltage - 0.5 +10.0 v v i all input voltages - 0.5 v dd1 + 0.5 v i ss ground supply current - 50 +50 ma i i , i o dc input or output current - 10 +10 ma p tot total power dissipation - 300 mw p out power dissipation per output - 30 mw t stg storage temperature - 65 +150 c
2004 may 17 42 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 16 dc characteristics v dd1 = 1.7 v to 3.3 v; v ss =0v; v lcd = 3.0 v to 9.0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v dd1 general supply voltage 1.7 - 3.3 v basic command set; when using rom look-up table (see section 13.10) 2.0 - 3.3 v v dd2, v dd3 supply voltage for the internal voltage generator 1.8 - 3.3 v v lcdin lcd supply voltage lcd voltage externally supplied (voltage generator disabled) -- 9.0 v v lcdout voltage multiplier output voltage lcd voltage internally generated (voltage generator enabled); note 1 -- 9.0 v v lcd(tol) tolerance of generated v lcd without calibration - 300 - +300 mv with calibration; note 2 - 70 - +70 mv i dd1 general supply current notes 3 and 4 0.5 1.5 5 m a notes 4 and 5 15 25 50 m a i dd2, i dd3 supply current for the internal voltage generator notes 3 and 4 0 0.5 1 m a notes 5 and 4 130 150 200 m a i dd(tot) total supply current (v dd1 +v dd2 +v dd3 ) notes 5 and 4 145 175 250 m a logic inputs; mf[2:0], v os [4:0], ds0, ext, ps[2:0], res and osc v il low-level input voltage v ss - 0.2v dd1 v v ih high-level input voltage 0.8v dd1 - v dd1 v i l leakage current v i =v dd or v ss - 1 - +1 m a column and row outputs r col column output resistance col 0 to col 127 v lcd =5v -- 5k w r row row output resistance row 0 to row 79 v lcd =5v -- 5k w v bias(col) bias tolerance voltage col 0 to col 127 - 100 0 +100 mv v bias(row) bias tolerance voltage row 0 to row 80 - 100 0 +100 mv lcd supply voltage generator tc0 v lcd temperature coef?cient 0 - 0 - / c tc1 v lcd temperature coef?cient 1 -- 0.16 10 - 3 - / c tc2 v lcd temperature coef?cient 2 -- 0.33 10 - 3 - / c tc3 v lcd temperature coef?cient 3 -- 0.50 10 - 3 - / c tc4 v lcd temperature coef?cient 4 -- 0.66 10 - 3 - / c tc5 v lcd temperature coef?cient 5 -- 0.833 10 - 3 - / c
2004 may 17 43 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 notes 1. the maximum possible v lcd voltage that may be generated is dependent on voltage, temperature and (display) load. 2. valid for values of temperature, v pr and tc used at calibration. 3. during power-down all static currents are switched off. 4. conditions are: v dd1 = 1.8 v, v dd2 = 2.7 v, v lcd = 8.05 v, voltage multiplier 4v dd2 , inputs at v dd1 or v ss , interface inactive, internal v lcd generation, v lcd output is loaded by 10 m a and t amb =25 c. 5. normal mode. 6. tc7 can only be used when v dd2 =v dd3 = 2.4 v or higher. 17 ac characteristics v dd1 = 1.7 v to 3.3 v; v ss =0v; v lcd = maximum 9.0 v; t amb = - 40 c to +85 c; note 1; unless otherwise specified. notes 1. all specified timings are based on 20 % and 80 % of v dd . 2. res may be low before v dd goes high. tc6 v lcd temperature coef?cient 6 -- 1.25 10 - 3 - / c tc7 v lcd temperature coef?cient 7 note 6 -- 1.66 10 - 3 - / c parallel interface; v dd1 = 1.8 v to 3.3 v v il low-level input voltage v ss - 0.2v dd1 v v ih high-level input voltage 0.8v dd1 - v dd1 v serial interface; v dd1 = 1.7 v to 3.3 v v il low-level input voltage v ss - 0.2v dd1 v v ih high-level input voltage 0.8v dd1 - v dd1 v i 2 c-bus interface; v dd1 = 1.8 v to 3.3 v i ol(sda) low-level output current at pin sda v ol = 0.4 v; v dd1 >2v -- 3ma v ol = 0.2v dd1 ; v dd1 <2v -- 2ma v il low-level input voltage v ss - 0.3v dd1 v v ih high-level input voltage 0.7v dd1 - v dd1 v output levels for all interfaces v ol low-level output voltage i ol = 0.5 ma v ss - 0.2v dd1 v v oh high-level output voltage i oh = - 0.5 ma 0.8v dd1 - v dd1 v symbol parameter conditions min. typ. max. unit f ext external clock frequency - 200 - khz f frame frame frequency t amb =25 c; v dd1 =2.4v546066hz 43 58 73 hz t vhrl v dd to res low see fig.43 0 (2) - 1 m s t rw res low pulse width see fig.43 500 -- ns symbol parameter conditions min. typ. max. unit
2004 may 17 44 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 18 parallel interface timing characteristics v dd1 = 1.8 v to 3.3 v; v ss =0v; v lcd = maximum 9.0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min. max. unit parallel bus timing; see figs 35 and 36 6800 series t su;dc data/ command set-up time 40 - ns t hd;dc data/ command hold time 20 - ns t cyc(ds) data strobe cycle time 1000 - ns t ds(l) data strobe low time 320 - ns t ds(h) data strobe high time 300 - ns t su;rw read/ wr ite set-up time 280 - ns t hd;rw read/ wr ite hold time 20 - ns t su;ce chip enable set-up time 280 - ns t hd;ce chip enable hold time 0 - ns t su;dat data set-up time 20 - ns t hd;dat data hold time 40 - ns t dat;acc data output access time - 280 ns t dat;oh data output disable time - 20 ns
2004 may 17 45 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw755 t su;dat t hd;dat t ds(h) t cyc(ds) t ds(l) t dat;acc t dat;oh t hd;dc t su;dc t hd;ce t hd;rw t su;ce t su;rw d0 to d7 (write) d0 to d7 (read) sce rw d/c e fig.35 parallel interface timing (6800-series) (read).
2004 may 17 46 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw756 t su;dat t hd;dat t ds(l) t cyc(ds) t ds(h) t dat;acc t dat;oh t hd;dc t su;dc t hd;rw t su;rw d0 to d7 (write) d0 to d7 (read) e d/c d/c, rw sce fig.36 parallel interface timing (6800-series) (write).
2004 may 17 47 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 19 serial interface timing characteristics v dd1 = 1.8 v to 3.3 v; v ss =0v; v lcd = maximum 9.0 v; t amb = - 40 c to +85 c; note 1; unless otherwise speci?ed. notes 1. all specified timings are based on 20 % and 80 % of v dd . 2. t h5 is the time from the previous sclk rising edge (irrespective of the state of sce) to the falling edge of sce. 3. sdout disable time for spi 3-line or 4-line interface. 4. sdout disable time for serial interface 3-line. 5. maximum values are for f sclk = 9 mhz. series resistance includes ito track + connector resistance + printed-circuit board. symbol parameter conditions min. max. unit 3-line and 4-line (spi and serial interface); see fig.37 to fig.40 f sclk clock frequency 9.00 - mhz t cyc clock cycle sclk 111 - ns t pwh1 sclk pulse width high 45 - ns t pwl1 sclk pulse width low 45 - ns t s2 sce set-up time 50 - ns t h2 sce hold time 45 - ns t pwh2 sce minimum high time 50 - ns t h5 sce start hold time note 2 50 - ns t s4 sdin set-up time 50 - ns t h4 sdin hold time 50 - ns t s3 data/ command set-up time 50 - ns t h3 data/ command hold time 50 - ns t s1 sdin set-up time 50 - ns t h1 sdin hold time 50 - ns t 1 sdout access time - 50 ns t 2 sdout disable time note 3 - 50 ns t 3 sce hold time 50 - ns t 4 sdout disable time note 4 25 100 ns c b capacitive load for sdo note 5 - 30 pf r b series resistance for sdo note 5 - 500 w
2004 may 17 48 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw757 t h1 t pwh1 t pwl1 t s1 t s2 t s2 t h2 t h5 t cyc (t h5 ) t pwh2 sce sclk sdata fig.37 3-line serial interface timing. handbook, full pagewidth mgw758 t h4 t pwh1 t pwl1 t h3 t s4 t s2 t s3 t s2 t h2 t h5 t cyc (t h5 ) t pwh2 sce d/c sclk sdata fig.38 4-line serial interface timing.
2004 may 17 49 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgw759 t 2 t 3 t 1 t h1 t s1 sce sclk sdout sdata fig.39 serial interface timing; read mode spi 3- or 4-line. handbook, full pagewidth mgw760 t 4 t 3 t 1 t h1 t s1 sce sclk sdout sdata fig.40 serial interface timing; read mode serial interface 3-line.
2004 may 17 50 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 20 i 2 c-bus interface timing characteristics v dd1 = 1.8 v to 3.3 v; v ss =0v; v lcd = maximum 9.0 v; t amb = - 40 c to +85 c; note 1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit fs-mode; see fig.41 f sclh sclh clock frequency 0 - 400 khz t su;sta set-up time (repeated) start condition 600 -- ns t hd;sta hold time (repeated) start condition 600 -- ns t low low period of the sclh clock 1300 -- ns t high high period of the sclh clock 600 -- ns t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 - 900 ns t r scl and sda rise time note 2 20 + 0.1c b - 300 ns t f scl and sda fall time note 2 20 + 0.1c b - 300 ns c b capacitive load represented by each bus line -- 400 pf t su;sto set-up time for stop condition 600 -- ns t sp tolerable spike width on bus -- 50 ns t buf bus free time between start and stop condition 1300 -- ns v nl noise margin at the low level for each connected device (including hysteresis) 0.1v dd1 -- v v nh noise margin at the high-level for each connected device (including hysteresis) 0.2v dd1 -- v hs-mode; see fig.42 f sclh sclh clock frequency 0 - 3.4 mhz t su;sta set-up time (repeated) start condition 160 -- ns t hd;sta hold time (repeated) start condition 160 -- ns t low low period of the sclh clock 160 -- ns t high high period of the sclh clock 60 -- ns t su;dat data set-up time 10 -- ns t hd;dat data hold time 20 - 70 ns t rcl rise time of the sclh signal 10 - 40 ns t rcl1 rise time of the sclh signal after the acknowledge bit 10 - 80 ns t fcl fall time of the sclh signal 10 - 40 ns t rda rise time of the sdah signal 10 - 80 ns t fcl1 fall time of the sclh signal 10 - 80 ns
2004 may 17 51 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 notes 1. all specified output timings are based on 20 % and 80 % of v dd1 . 2. c b = 100 pf total capacitance of one bus line. t su;sto set-up time for stop condition 160 -- ns c b2 capacitive load for the sdah and sclh lines note 2 -- 100 pf c b capacitive load for the sdah + sda line and sclh + scl line note 2 -- 400 pf t sp tolerable spike width on bus -- 5ns v nl noise margin at the low-level for each connected device (including hysteresis) 0.1v dd1 -- v v nh noise margin at the high-level for each connected device (including hysteresis) 0.2v dd1 -- v symbol parameter conditions min. typ. max. unit handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.41 i 2 c-bus timing diagram (fs-mode). s = start. sr = start repeated. p = stop.
2004 may 17 52 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth mgk871 sdah sr sr p sclh = mcs current source pull-up = rp resistor pull-up t fda t rda t hd;sta t su;dat t rcl t low t high t hd;dat t low t high t rcl1 t fcl t su;sto t rcl1 (1) (1) t su;sta fig.42 i 2 c-bus timing diagram (hs-mode). (1) rising edge of the first sclh clock pulse after an acknowledge bit. handbook, full pagewidth mgw761 t vhrl t rw t rw t rw t rw res v dd res v dd fig.43 reset timing.
2004 may 17 53 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 21 application information semiconductors are light sensitive. exposure to light sources can cause malfunction of the ic. in the application it is therefore required to protect the ic from light. the protection has to be done on all sides of the ic, i.e. front, rear and all edges. the pinning of the pcf8811 has an optimum design for single plane wiring e.g. for chip-on-glass display modules. display size: 80 128 pixels. for further application information refer to philips application note an10170. handbook, full pagewidth mgw762 display 80 128 pixels v dd2 v dd1 i/o c vlcd v ss1 v ss2 v lcdin v lcdout v lcdsense pcf8811 v dd v ss c vdd fig.44 application diagram: internal charge pump is used and a single supply. handbook, full pagewidth v lcdin v lcdout v lcdsense display 80 128 pixels mgw763 v dd2 v dd1 v dd2 v dd1 i/o v ss c vlcd c vdd2 v ss1 v ss2 c vdd1 pcf8811 fig.45 application diagram: internal charge pump is used and two separate supplies (v dd1 and v dd2 ).
2004 may 17 54 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 the required minimum value for the external capacitors in an application with the pcf8811 are: c vlcd =1 m f to 4.7 m f depending on the application c vdd , c vdd1 and c vdd2 =1 m f. for these capacitors higher values can be used. handbook, full pagewidth mgw764 display 80 128 pixels v dd2 v dd1 i/o v ss1 v ss2 v lcdin v lcdout v lcdin v lcdsense pcf8811 v dd v ss c vdd fig.46 application diagram: external high voltage is used.
2004 may 17 55 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 22 module maker programming the one time programmable (otp) technology is implemented on the pcf8811. it enables the module maker to program some extended features of the pcf8811 after it has been assembled on an lcd module. programming is made under the control of the interfaces and the use of one special pin. this pin must be made available on the module glass but need not to be accessed by the set maker. the pcf8811 features 3 module maker programmable parameters: v lcd calibration temperature coefficient selection seal bit. 22.1 v lcd calibration the first feature included is the ability to adjust the v lcd voltage with a 5-bit code (mmvopcal). this code is implemented in twos complement notation giving rise to a positive or negative offset to the v pr register. this is in the same manner as the on-glass calibration pins v os . in theory, both may be used together but it is recommended that the v os pins are tied to v ss when otp calibration is being used. this will set them to a default offset of zero. if both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result otherwise the resultant value will be undefined. the final adder in the circuit has underflow and overflow protection. in the event of an overflow, the output will be clamped to 255; during an underflow the output will be clamped to 0. the final control to the high voltage generator, v op , will be the sum of all the calibration registers and pins. the v lcd equation (4) or (5) given in section 13.10 must be extended to include the otp calibration, as follows; (7) the possible mmvopcal[4:0] values are the same as the v os [4:0] values; see table 12. v lcd tt cut = () av os [4:0] mmvopcal[4:0] v + op [7:0] + ( ) b + = handbook, full pagewidth mgu287 otp v lcd calibration: 5-bit offset mmvopcal [ 4:0 ] v op [7:0] range: 0 to + 255 range - 16 to + 15 range - 16 to + 15 range 0 to + 255 usable range + 32 to + 255 to high voltage generator laser trim pins: 5-bit offset v os [ 4:0 ] v pr register: 8-bit value v pr [ 7:0 ] + + fig.47 v lcd calibration.
2004 may 17 56 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 22.2 temperature coef?cient selection the second feature is an otp factory default setting for the temperature coefficient selection (mmtc) in the basic command set. this 3-bit value will be loaded from otp after leaving the power-save mode or by the refresh command. the idea of this feature is to provide, in the basic command set, the complete set of temperature coefficients without an additional command. in the extended command set the temperature coefficient can be programmed as given in table 16. 22.3 seal bit the module maker programming is performed in a special mode: the calibration mode (calmm). this mode is entered via a special interface command, calmm. to prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. this seal bit, once programmed, can not be reversed, thus further changes in programmed values are not possible. applying the programming voltages when not in calmm mode will have no effect on the programmed values. table 23 seal bit de?nition 22.4 otp architecture the otp circuitry in the pcf8811 contains 9 bits of data: 5 for v lcd calibration (mmvopcal), 3 for the temperature coefficient default setting in the basic command set mmtc and 1 seal bit. the circuitry for 1-bit is called an otp slice. each otp slice consists of 2 main parts: the otp cell (a non-volatile memory cell) and the shift register cell (a flip-flop). the otp cells are only accessible through their shift register cells: on the one hand both reading from and writing to the otp cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. the basic otp architecture is shown in fig.48. this otp architecture allows the following operations: 1. reading data from the otp cells. the content of the non-volatile otp cells is transferred to the shift register where upon it may affect the pcf8811 operation. 2. writing data to the otp cells. first, all 9 bits of data are shifted into the shift register via the interface. the content of the shift register is then transferred to the otp cells (there are some limitations related to storing data in these cells; see section 22.7). 3. checking calibration without writing to the otp cells. shifting data into the shift register allows the effects on the v lcd voltage to be observed. the reading of data from the otp cells is initiated by either: exit from power-save mode the refresh command (power control). it should be noted that in both cases the reading operation needs up to 5 ms to complete. the shifting of data into the shift register is performed in the special mode calmm. in the pcf8811 the calmm mode is entered by the calmm command. once in the calmm mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. after transmitting the last (9th) bit and exiting the calmm mode, the serial interface will return to the normal mode and all other commands can be sent. care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the calmm mode, otherwise the bits will be in the wrong positions. in the shift register the value of the seal bit is, like the others, always zero at reset. to ensure that the security feature works correctly, the calmm command is disabled until a refresh has been performed. once the refresh is completed, the seal bit value in the shift register will be valid and permission to enter the calmm mode can thus be determined. the 9 bits are shifted into the shift register in a predefined order: first 5 bits of mmvopcal[4:0], 3 bits for mmtc[2:0] and lastly the seal bit. the msb is always first, thus the first bit shifted is mmvopcal[4] and the two last bits are mmtc[0] and the seal bit. seal bit action 0 possible to enter calibration mode 1 calibration mode disabled
2004 may 17 57 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 22.5 interface commands these instructions are in addition to those indicated in table 5. table 24 additional instructions; note 1 note 1. x = dont care. 22.5.1 calmm this instruction puts the device in calibration mode. this mode enables the shift register for loading and allows programming of the non-volatile otp cells to take place. if the seal bit is set then this mode cannot be accessed and the instruction will be ignored. once in calibration mode all commands are interpreted as shift register data. the mode can only be exited by sending data with bit d7 set to logic 0. reset will also clear this mode. each shift register data byte is preceded by d/ c = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. bit d7 is the continuation bit (d7 = 1 remain in calmm mode, d7 = 0 exit calmm mode). bit d0 is the data bit and its value is shifted into the otp shift register (on the falling edge of sclk). name ext d/ cr/ w command byte action d7 d6 d5 d4 d3 d2 d1 d0 calmm x 0 0 1 0 0 0 0 0 1 0 enter calmm mode power control (refresh) x 0 0 0 0 1 0 1 pc1 pc0 1 switch hvgen on/off to force a refresh of the shift register handbook, full pagewidth data to the circuit for configuration and calibration shift register flip-flop otp slice otp cell shift register shift register data input read data from the otp cell write data to the otp cell otp cells mgu289 fig.48 basic otp architecture.
2004 may 17 58 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 22.5.2 r efresh the action of the refresh instruction is to force the otp shift register to re-load from the non-volatile otp cells. this instruction takes up to 5 ms to complete. during this time all other instructions may be sent. in the pcf8811 the refresh instruction is associated with the power control instruction so that the shift register is automatically refreshed every time the high voltage generator is enabled or disabled. it should be noted however, that if this instruction is sent while in the power-save mode, the pc[1:0] bits will be updated but the refreshing will be ignored. 22.6 example of ?lling the shift register an example of the sequence of commands and data is shown in table 25. in this example the shift register is filled with the following data: mmvopcal = - 4 (11100 bin), mmtc = 2 (010 bin) and the seal bit is 0. it is assumed that the pcf8811 has just been reset. after transmitting the last bit the pcf8811 can exit or remain in the calmm mode (see step 1). it should be noted that while in calmm mode the interface does not recognize commands in the normal sense. after this sequence has been applied it is possible to observe the impact of the data shifted in. the described sequence is, however, not useful for otp programming because the number of bits with the value logic 1 is greater than that allowed for programming; see section 22.7. figure 49 shows the shift register after this action. table 25 example sequence for ?lling the shift register; note 1 notes 1. x = dont care. 2. the data for the bits is not in the correct shift register position until all bits have been sent. step ext d/ cr/ w d7 d6 d5 d4 d3 d2 d1 d0 action 1 x 0 0 1 1 1 0 0 0 0 1 exit power-down 2 wait 5 ms for refresh to take effect 3 x 0 0 1 0 0 0 0 0 1 0 enter calmm mode 4 x 0 0 1 x x x x x x 1 shift in data. mmvopcal[4] is ?rst bit; note 2 5 x 0 0 1 x x x x x x 1 mmvopcal[3] 6 x 0 0 1 x x x x x x 1 mmvopcal[2] 7 x 0 0 1 x x x x x x 0 mmvopcal[1] 8 x 0 0 1 x x x x x x 0 mmvopcal[0] 9 x 0 0 1 x x x x x x 0 mmtc[2] 10 x 0 0 1 x x x x x x 1 mmtc[1] 11 x 0 0 1 x x x x x x 0 mmtc[0] 12 x 0 0 0 x x x x x x 0 seal bit; exit calmm mode an alternative ending could be to stay in calmm mode 13 x 0 0 1 x x x x x x 0 seal bit; remain in calmm mode
2004 may 17 59 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 handbook, full pagewidth msb lsb shifting direction 0 mgw765 mmtc [ 2:0 ] seal bit = 0 1 0 msb lsb 0 mmvopcal [ 4:0 ] otp shift register 0 1 1 1 fig.49 shift register contents after example sequence of table 25. 22.7 programming ?ow programming is achieved whilst in calmm mode and with the application of the programming voltages. as mentioned previously, the data for programming the otp cell is contained in the corresponding shift register cell. the shift register cell must be loaded with a logic 1 in order to program the corresponding otp cell. if the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. once programmed, an otp cell cannot be de-programmed. an already programmed cell, i.e. an otp cell containing a logic 1, must not be re-programmed. during programming a substantial current flows in the v lcdin pin. for this reason it is recommended to program only one otp cell at a time. this is achieved by filling all but one shift register cells with logic 0. it should be noted that the programming specification refers to the voltages at the chip pins, contact resistance must therefore be considered by the user. an example sequence of commands and data for otp programming is given in table 26. the order for programming cells is not significant. however, it is recommended that the seal bit is programmed last. once this bit has been programmed it will not be possible to re-enter the calmm mode. it is assumed that the pcf8811 has just been reset.
2004 may 17 60 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 26 sequence for otp programming; note 1 note 1. x = dont care. 22.8 programming speci?cation table 27 programming speci?cation; see fig.50 step ext d/ cr/ w d7 d6 d5 d4 d3 d2 d1 d0 action 1 x0011100001e xit power-save 2 wait 5 ms for refresh to take effect 3 x0010101001 re-enter power-down (don = 0) 4 x0010000010 enter calmm mode 5 x0010 xxxxx1 shift in data; mmvopcal[4] is ?rst bit 6 x0010 xxxxx1mmv opcal[3] 7 x0010 xxxxx1mmv opcal[2] 9 x0010 xxxxx0mmv opcal[1] 10 x0010 xxxxx0mmv opcal[0] 11 x0010 xxxxx0 mmtc[2] 12 x0010 xxxxx1 mmtc[1] 13 x0010 xxxxx0 mmtc[0] 14 x0011 xxxxx0 seal bit; remain in calmm mode 15 apply programming voltage at pins v otpprog and v lcdin according to section 22.8 repeat steps 5 to 14 for each bit that should be programmed to 1 16 apply external reset symbol parameter conditions min. typ. max. unit v otpprog voltage applied to pin v otpprog relative to v ss1 programming active; note 1 11.0 11.5 12.0 v programming inactive; note 1 v ss - 0.2 0 +0.2 v v lcdin voltage applied to pin v lcdin relative to v ss1 programming active; notes 1 and 2 9 9.5 10 v programming inactive; notes 1 and 2 v dd2 - 0.2 v dd2 4.5 v i lcdin current drawn by v lcdin during programming when programming a single bit to logic 1 - 850 1000 m a i votpprog current drawn by v otpprog during programming - 100 200 m a t amb(prog) ambient temperature during programming 02540 c t su;sclk set-up time of internal data after last clock 1 --m s
2004 may 17 61 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 notes 1. the voltage drop across the ito track and zebra connector must be taken into account to guarantee a sufficiently high voltage at the chip pins. 2. the power-down mode (don = 0 and dal = 1) and calmm mode must be active while the v lcdin pin is being driven. t hd;sclk hold time of internal data before next clock 1 --m s t su;votpprog set-up time of v otpprog prior to programming 1 - 10 m s t hd;votpprog hold time of v otpprog after programming 1 - 10 ms t pw pulse width of programming voltage 100 120 200 ms symbol parameter conditions min. typ. max. unit handbook, full pagewidth sclk t su;sclk t pw t hd;sclk t hd;votpprog t su;votprog mgw766 v votpprog v lcdin fig.50 programming waveforms.
2004 may 17 62 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 23 chip information the pcf8811 is manufactured in n-well cmos technology. the substrate is at v ss potential. 24 bonding pad locations table 28 bonding pad information pad rows/cols side interface side unit pad pitch min. 51.84 min. 54 m m pad size (aluminium) 42.84 105 50 100 m m bump dimensions 31.9 100 17.5 ( 5) 34 95 17.5 ( 5) m m wafer thickness (excluding bumps) 381 ( 25) m m handbook, halfpage mgw767 12.45 mm 2.31 mm pcf8811 x y pitch fig.51 chip size and pad pitch. mgw768 handbook, halfpage x center y center 90 m m fig.52 shape of alignment mark (90 m m diameter).
2004 may 17 63 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 table 29 bonding pad locations all x and y co-ordinates are referenced to the centre of the chip (dimensions in m m; see fig.53). symbol pad co-ordinates xy dummy_slanted 1 6092 1030 alignment mark 2 5995 1017 dummy 3 5876 1030 dummy 4 5822 1030 dummy 5 5768 1030 dummy 6 5714 1030 dummy 7 5660 1030 dummy 8 5390 1030 mf2 9 5012 1030 mf1 10 4850 1030 mf0 11 4688 1030 ds0 12 4526 1030 osc 13 4364 1030 ext 14 4094 1030 ps0 15 3932 1030 ps1 16 3770 1030 ps2 17 3608 1030 v ss(tie off) 18 3446 1030 sdahout 19 2960 1030 sdah 20 2420 1030 sdah 21 2366 1030 sclh/ sce 22 1826 1030 sclh/ sce 23 1772 1030 v otpprog 24 1664 1030 v otpprog 25 1610 1030 v otpprog 26 1556 1030 res 27 1448 1030 d/ c 28 1232 1030 r/ w 29 962 1030 e 30 800 1030 v dd(tie off) 31 638 1030 db0 32 476 1030 db1 33 314 1030 db2 34 152 1030 db3 35 - 10 +1030 db4 36 - 172 +1030 db5 37 - 334 +1030 db6 38 - 550 +1030 db7 39 - 712 +1030 v dd1 40 - 874 +1030 v dd1 41 - 928 +1030 v dd1 42 - 982 +1030 v dd1 43 - 1036 +1030 v dd1 44 - 1090 +1030 v dd1 45 - 1144 +1030 v dd2 46 - 1198 +1030 v dd2 47 - 1252 +1030 v dd2 48 - 1306 +1030 v dd2 49 - 1360 +1030 v dd2 50 - 1414 +1030 v dd2 51 - 1468 +1030 v dd2 52 - 1522 +1030 v dd2 53 - 1576 +1030 v dd2 54 - 1630 +1030 v dd2 55 - 1684 +1030 v dd3 56 - 1738 +1030 v dd3 57 - 1792 +1030 v dd3 58 - 1846 +1030 v dd3 59 - 1900 +1030 v dd3 60 - 1954 +1030 v ss1 61 - 2062 +1030 v ss1 62 - 2116 +1030 v ss1 63 - 2170 +1030 v ss1 64 - 2224 +1030 v ss1 65 - 2278 +1030 v ss1 66 - 2332 +1030 v ss1 67 - 2386 +1030 v ss1 68 - 2440 +1030 v ss1 69 - 2494 +1030 v ss1 70 - 2548 +1030 v ss2 71 - 2602 +1030 v ss2 72 - 2656 +1030 symbol pad co-ordinates xy
2004 may 17 64 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 v ss2 73 - 2710 +1030 v ss2 74 - 2764 +1030 v ss2 75 - 2818 +1030 v ss2 76 - 2872 +1030 v ss2 77 - 2926 +1030 v ss2 78 - 2980 +1030 v ss2 79 - 3034 +1030 v ss2 80 - 3088 +1030 t5 81 - 3250 +1030 t2 82 - 3304 +1030 t1 83 - 3466 +1030 t4 84 - 3628 +1030 t3 85 - 3790 +1030 v os4 86 - 4060 +1030 v os3 87 - 4222 +1030 v os2 88 - 4384 +1030 v os1 89 - 4654 +1030 v os0 90 - 4816 +1030 v lcdout 91 - 4924 +1030 v lcdout 92 - 4978 +1030 v lcdout 93 - 5032 +1030 v lcdout 94 - 5086 +1030 v lcdout 95 - 5140 +1030 v lcdout 96 - 5194 +1030 v lcdout 97 - 5248 +1030 v lcdout 98 - 5302 +1030 v lcdout 99 - 5356 +1030 v lcdsense 100 - 5410 +1030 v lcdin 101 - 5464 +1030 v lcdin 102 - 5518 +1030 v lcdin 103 - 5572 +1030 v lcdin 104 - 5626 +1030 v lcdin 105 - 5680 +1030 v lcdin 106 - 5734 +1030 v lcdin 107 - 5788 +1030 alignment mark 108 - 5904 +1017 dummy 109 - 6004 +1030 symbol pad co-ordinates xy dummy 110 - 6058 +1030 dummy 111 - 6112 +1030 dummy 112 - 6129.24 - 1032.5 dummy 113 - 6077.40 - 1032.5 dummy 114 - 6025.56 - 1032.5 r79 115 - 5973.72 - 1032.5 r78 116 - 5921.88 - 1032.5 r77 117 - 5870.04 - 1032.5 r76 118 - 5818.20 - 1032.5 r75 119 - 5766.36 - 1032.5 r74 120 - 5714.52 - 1032.5 r73 121 - 5662.68 - 1032.5 r72 122 - 5610.84 - 1032.5 r71 123 - 5559.00 - 1032.5 r70 124 - 5507.16 - 1032.5 r69 125 - 5455.32 - 1032.5 r68 126 - 5403.48 - 1032.5 r67 127 - 5351.64 - 1032.5 r66 128 - 5299.80 - 1032.5 r65 129 - 5247.96 - 1032.5 r64 130 - 5196.12 - 1032.5 r63 131 - 5144.28 - 1032.5 r62 132 - 5092.44 - 1032.5 r61 133 - 5040.60 - 1032.5 r60 134 - 4988.76 - 1032.5 r59 135 - 4936.92 - 1032.5 r58 136 - 4885.08 - 1032.5 r57 137 - 4833.24 - 1032.5 r56 138 - 4781.40 - 1032.5 r55 139 - 4729.56 - 1032.5 r54 140 - 4677.72 - 1032.5 r53 141 - 4625.88 - 1032.5 r52 142 - 4574.04 - 1032.5 r51 143 - 4522.20 - 1032.5 r50 144 - 4470.36 - 1032.5 r49 145 - 4418.52 - 1032.5 r48 146 - 4366.68 - 1032.5 symbol pad co-ordinates xy
2004 may 17 65 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 r47 147 - 4314.84 - 1032.5 r46 148 - 4263 - 1032.5 r45 149 - 4211.16 - 1032.5 r44 150 - 4159.32 - 1032.5 r43 151 - 4107.48 - 1032.5 r42 152 - 4055.64 - 1032.5 r41 153 - 4003.80 - 1032.5 r40 154 - 3951.96 - 1032.5 r80 (duplicate r79) 155 - 3900.12 - 1032.5 c0 156 - 3640.92 - 1032.5 c1 157 - 3589.08 - 1032.5 c2 158 - 3537.24 - 1032.5 c3 159 - 3485.40 - 1032.5 c4 160 - 3433.56 - 1032.5 c5 161 - 3381.72 - 1032.5 c6 162 - 3329.88 - 1032.5 c7 163 - 3278.04 - 1032.5 c8 164 - 3226.20 - 1032.5 c9 165 - 3174.36 - 1032.5 c10 166 - 3122.52 - 1032.5 c11 167 - 3070.68 - 1032.5 c12 168 - 3018.84 - 1032.5 c13 169 - 2967 - 1032.5 c14 170 - 2915.16 - 1032.5 c15 171 - 2863.32 - 1032.5 c16 172 - 2811.48 - 1032.5 c17 173 - 2759.64 - 1032.5 c18 174 - 2707.80 - 1032.5 c19 175 - 2655.96 - 1032.5 c20 176 - 2604.12 - 1032.5 c21 177 - 2552.28 - 1032.5 c22 178 - 2500.44 - 1032.5 c23 179 - 2448.60 - 1032.5 c24 180 - 2396.76 - 1032.5 c25 181 - 2344.92 - 1032.5 c26 182 - 2293.08 - 1032.5 c27 183 - 2241.24 - 1032.5 symbol pad co-ordinates xy c28 184 - 2189.40 - 1032.5 c29 185 - 2137.56 - 1032.5 c30 186 - 2085.72 - 1032.5 c31 187 - 2033.88 - 1032.5 c32 188 - 1878.36 - 1032.5 c33 189 - 1826.52 - 1032.5 c34 190 - 1774.68 - 1032.5 c35 191 - 1722.84 - 1032.5 c36 192 - 1671.00 - 1032.5 c37 193 - 1619.16 - 1032.5 c38 194 - 1567.32 - 1032.5 c39 195 - 1515.48 - 1032.5 c40 196 - 1463.64 - 1032.5 c41 197 - 1411.80 - 1032.5 c42 198 - 1359.96 - 1032.5 c43 199 - 1308.12 - 1032.5 c44 200 - 1256.28 - 1032.5 c45 201 - 1204.44 - 1032.5 c46 202 - 1152.60 - 1032.5 c47 203 - 1100.76 - 1032.5 c48 204 - 1048.92 - 1032.5 c49 205 - 997.08 - 1032.5 c50 206 - 945.24 - 1032.5 c51 207 - 893.40 - 1032.5 c52 208 - 841.56 - 1032.5 c53 209 - 789.72 - 1032.5 c54 210 - 737.88 - 1032.5 c55 211 - 686.04 - 1032.5 c56 212 - 634.20 - 1032.5 c57 213 - 582.36 - 1032.5 c58 214 - 530.52 - 1032.5 c59 215 - 478.68 - 1032.5 c60 216 - 426.84 - 1032.5 c61 217 - 375 - 1032.5 c62 218 - 323.16 - 1032.5 c63 219 - 271.32 - 1032.5 c64 220 - 115.80 - 1032.5 symbol pad co-ordinates xy
2004 may 17 66 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 c65 221 - 63.96 - 1032.5 c66 222 - 12.12 - 1032.5 c67 223 +39.72 - 1032.5 c68 224 +91.56 - 1032.5 c69 225 +143.40 - 1032.5 c70 226 +195.24 - 1032.5 c71 227 +247.08 - 1032.5 c72 228 +298.92 - 1032.5 c73 229 +350.76 - 1032.5 c74 230 +402.60 - 1032.5 c75 231 +454.44 - 1032.5 c76 232 +506.28 - 1032.5 c77 233 +558.12 - 1032.5 c78 234 +609.96 - 1032.5 c79 235 +661.80 - 1032.5 c80 236 +713.64 - 1032.5 c81 237 +765.48 - 1032.5 c82 238 +817.32 - 1032.5 c83 239 +869.16 - 1032.5 c84 240 +921.00 - 1032.5 c85 241 +972.84 - 1032.5 c86 242 +1024.68 - 1032.5 c87 243 +1076.52 - 1032.5 c88 244 +1128.36 - 1032.5 c89 245 +1180.20 - 1032.5 c90 246 +1232.04 - 1032.5 c91 247 +1283.88 - 1032.5 c92 248 +1335.72 - 1032.5 c93 249 +1387.56 - 1032.5 c94 250 +1439.40 - 1032.5 c95 251 +1491.24 - 1032.5 c96 252 +1646.76 - 1032.5 c97 253 +1698.60 - 1032.5 c98 254 +1750.44 - 1032.5 c99 255 +1802.28 - 1032.5 c100 256 +1854.12 - 1032.5 c101 257 +1905.96 - 1032.5 symbol pad co-ordinates xy c102 258 +1957.80 - 1032.5 c103 259 +2009.64 - 1032.5 c104 260 +2061.48 - 1032.5 c105 261 +2113.32 - 1032.5 c106 262 +2165.16 - 1032.5 c107 263 +2217.00 - 1032.5 c108 264 +2268.84 - 1032.5 c109 265 +2320.68 - 1032.5 c110 266 +2372.52 - 1032.5 c111 267 +2424.36 - 1032.5 c112 268 +2476.20 - 1032.5 c113 269 +2528.04 - 1032.5 c114 270 +2579.88 - 1032.5 c115 271 +2631.72 - 1032.5 c116 272 +2683.56 - 1032.5 c117 273 +2735.40 - 1032.5 c118 274 +2787.24 - 1032.5 c119 275 +2839.08 - 1032.5 c120 276 +2890.92 - 1032.5 c121 277 +2942.76 - 1032.5 c122 278 +2994.60 - 1032.5 c123 279 +3046.44 - 1032.5 c124 280 +3098.28 - 1032.5 c125 281 +3150.12 - 1032.5 c126 282 +3201.96 - 1032.5 c127 283 +3253.80 - 1032.5 r0 284 +3461.16 - 1032.5 r1 285 +3513.00 - 1032.5 r2 286 +3564.84 - 1032.5 r3 287 +3616.68 - 1032.5 r4 288 +3668.52 - 1032.5 r5 289 +3720.36 - 1032.5 r6 290 +3772.20 - 1032.5 r7 291 +3824.04 - 1032.5 r8 292 +3875.88 - 1032.5 r9 293 +3927.72 - 1032.5 r10 294 +3979.56 - 1032.5 symbol pad co-ordinates xy
2004 may 17 67 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 r11 295 +4031.40 - 1032.5 r12 296 +4083.24 - 1032.5 r13 297 +4135.08 - 1032.5 r14 298 +4186.92 - 1032.5 r15 299 +4238.76 - 1032.5 r16 300 +4290.60 - 1032.5 r17 301 +4342.44 - 1032.5 r18 302 +4394.28 - 1032.5 r19 303 +4446.12 - 1032.5 r20 304 +4497.96 - 1032.5 r21 305 +4549.80 - 1032.5 r22 306 +4601.64 - 1032.5 r23 307 +4653.48 - 1032.5 r24 308 +4705.32 - 1032.5 r25 309 +4757.16 - 1032.5 r26 310 +4809 - 1032.5 r27 311 +4860.84 - 1032.5 r28 312 +4912.68 - 1032.5 r29 313 +4964.52 - 1032.5 r30 314 +5016.36 - 1032.5 symbol pad co-ordinates xy r31 315 +5068.20 - 1032.5 r32 316 +5120.04 - 1032.5 r33 317 +5171.88 - 1032.5 r34 318 +5223.72 - 1032.5 r35 319 +5275.56 - 1032.5 r36 320 +5327.40 - 1032.5 r37 321 +5379.24 - 1032.5 r38 322 +5431.08 - 1032.5 r39 323 +5482.92 - 1032.5 dummy 324 +5638.44 - 1032.5 dummy 325 +5690.28 - 1032.5 dummy 326 +5742.12 - 1032.5 dummy 327 +5793.96 - 1032.5 dummy 328 +5845.80 - 1032.5 dummy 329 +5897.64 - 1032.5 dummy 330 +5949.48 - 1032.5 dummy 331 +6001.32 - 1032.5 dummy 332 +6053.16 - 1032.5 dummy 333 +6105.00 - 1032.5 symbol pad co-ordinates xy
2004 may 17 68 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 mgw769 v os0 v os1 v os2 v os3 v os4 t3 t4 t1 t2 t5 db7/sdata db6/sclk db5/sdo db4 db3/sa1 db2/sa0 db1 db0 v dd1 * e/rd r/w / wr d/c res sdahout ps2 ps1 ps0 ext osc ds0 mf0 mf1 mf2 v lcdin v lcdsense v lcdout v dd3 v dd1 v otpprog sclh/sce sdah v ss1 v dd2 v ss2 pcf8811 x y 0, 0 v ss1 * fig.53 bonding pad location (viewed from bump side). * v ss1* and v dd1* for local tie offs.
2004 may 17 69 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 25 device protection diagram handbook, full pagewidth mgw770 v dd1 v dd1 v ss1 v ss2 v ss1 t3, t4, v ss1 * , v dd * v ss1 v ss1 v dd1 osc, res, rd, d/c, ps [ 2:0 ], t1, t2, t5, e v lcdout v ss1 v lcdin , v lcdsense v ss1 v dd2 v ss1 v ss2 v lcdin v ss1 v dd1 db [ 7:0 ] , sclk, sdata, sdo, sa1, sa0, r/w, wr v ss1 v dd1 v ss1 v otpprog v ss1 lcd outputs i 2 c-bus pins v dd3 v ss1 fig.54 device protection diagram. for test purposes only: the maximum forward current is 5 ma. the maximum reverse voltage is 5 v.
2004 may 17 70 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 26 tray information handbook, full pagewidth mgu295 d f e x y a 1,1 x,1 2,1 1,2 1,3 1,y x,y 2,2 3,1 c b fig.55 tray details. table 30 tray dimensions handbook, halfpage mgw771 pcf8811-1 fig.56 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientation and position of the type name on the die surface. dim. description value a pocket pitch; x direction 13.77 mm b pocket pitch; y direction 4.45 mm c pocket width; x direction 12.55 mm d pocket width; y direction 2.41 mm e tray width; x direction 50.80 mm f tray width; y direction 50.80 mm x number of pockets in x direction 3 y number of pockets in y direction 10
2004 may 17 71 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 27 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 28 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 29 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 may 17 72 philips semiconductors product speci?cation 80 128 pixels matrix lcd driver pcf8811 bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. 30 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r15/03/pp 73 date of release: 2004 may 17 document order number: 9397 750 13144

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